ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 53

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ADC Sample time and conversion time are programmable. The table below should be used to calculate
the above timings.
20.5 - AC Characteristics
20.5.1 - Test Waveforms
Figure 16 : Input / output waveforms
Figure 17 : Float waveforms
ADCON.15|14 (ADCTC)
For timing purposes a port pin is no longer floating when V
It begins to float when a 100mV change from the loaded V
6. During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference
voltage source must allow the capacitance to reach its respective voltage level within t
from the programmed conversion timing.
7. Partially tested, guaranteed by design characterization.
8. To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at
the ADC input. The cut-off frequency of this filter must be twice the highest conversion frequency used in the application as described
in the formula:
f
where t
t
cut-off
c app
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
V
= 14 t
0.45V
= 2 / t
Load
2.4V
c app
00
01
10
11
CC
c app
is the shorter conversion time used in the application, calculated with the following formula:
V
V
+ t
Load
Load
Conversion Time
S
+ 4 TCL (= 14 t
+0.1V
-0.1V
Conversion clock t
Reserved, do not use
CC
+ 2 t
TCL x 24
TCL x 96
TCL x 48
SC
0.2V
0.2V
+ 4 TCL).
DD
DD
IH
+0.9
-0.1
CC
Test Points
min for a logic ‘1’ and V
Reference
Timing
Points
V
V
OL
OH
ADCON.13|12 (ADSTC)
0.2V
0.2V
DD
DD
OH
LOAD
-0.1
+0.9
00
01
10
11
/V
OL
changes of 100mV.
level occurs (I
CC
IL
Sample Time
. The maximum internal resistance results
max for a logic ‘0’.
V
V
Sample clock t
OL
OH
OH
+0.1V
-0.1V
/I
OL
t
t
t
CC
CC
CC
t
CC
= 20mA).
x 2
x 4
x 8
ST10F168
SC
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