ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 13

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5 - FLASH MEMORY
The ST10F168 provides 256K Byte of an
electrically erasable and reprogrammable Flash
Memory on-chip.
The Flash Memory can be used both for code and
data storage. It is organized into four 32-bit wide
blocks allowing even double Word instructions to
be fetched in one machine cycle. The four blocks
of size16K, 48K, 96K and 96K Byte can be erased
and reprogrammed individually (see Table 2 and
Table 3).
The Flash Memory can be programmed in a pro-
gramming board or in the target system which
provides high system flexibility. The algorithms to
program or erase the flash memory are embed-
ded in the Flash Memory itself (ST Embedded
Algorithm Kernel, or STEAK
To start a program / erase operation, the user’s
software has just to load GPRs with the address
and data to be programmed, or sector to be
erased. STEAK uses embedded routines, which
V
Q3 version T
Table 2 : Flash Memory Characteristics
Table 3 : Flash Memory Bank Organisation
Symbol
DD
t
t
Bank
t
f
SPRG
DPRG
EBNK
t
Cyc
CPU
RET
0
1
2
3
= 5V
000000h to 003FFFh
004000h to 007FFFh + 018000h to 01FFFFh
020000h to 037FFFh
038000h to 04FFFFh
CPU Frequency during
erasing / programming operation
Erasing / Programming Cycles
Single Word Programming Time
Double Word Programming Time
Sector Erasing Time
Data Retention Time
10%, V
A
= -40 C, + 125 C.
PP
Parameter
= 12V
Addresses (segment 0)
TM
).
5%, V
SS
= 0V, f
f
f
Defectivity below 1ppm / year
f
f
CPU
CPU
CPU
CPU
= 25MHz
= 25MHz
= 25MHz
= 25MHz
CPU
Test Conditio ns
= 25MHz, for Q6 version : T
check the validity of the programmed parameters,
decode and then execute the programming or
erase command. During operation, the STEAK
routines carry out checks and retries to verify
proper cell programming or erasing. When an
error occurs, STEAK returns an error-code which
identifies the cause of the error.
A Flash Memory protection option prevents the
read-back of the Flash Memory contents from
external memory, or from on-chip RAM. Code
operation from within the Flash continues as nor-
mal.
The first bank (16K Byte) and part of the second
bank (16K Byte out of 48K Byte) of the on-chip
Flash Memory of the ST10F168 can be mapped
to either segment 0 (addresses 00000h to
07FFFh) or to segment 1 (addresses 10000h to
17FFFh) during the initialization phase. External
memory can be used for additional system
flexibility.
Addresses (segment 1)
014000h to 01FFFFh
020000h to 03FFFFh
038000h to 04FFFFh
010000h to 013FFFh
Min.
20
5
-
-
-
-
A
Typ.
= -40 C, +85 C and for
40
40
3
-
-
-
Max.
1500
1500
10K
32
15
Size (Byte)
-
ST10F168
16K
48K
96K
96K
MHz
year
Unit
s
13/74
s
s