EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 711
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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Part Number
Manufacturer
Quantity
Price
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AC97SYNC
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8088_00A4 - Read/Write
Sync Control Register. The AC’97 Sync Controller register is a read / write
register that controls various functions within the AC’97 Controller of the
SYNC port. All the register bits are cleared to “0” when reset.
RSVD:
EFORCES:
FORCEDSYNC:
TIMEDSYNC:
27
11
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
Reserved. Unknown During Read.
Enable for Forced SYNC bit
1 - FORCEDSYNC become active
0 - FORCEDSYNC has no effect.
If EFORCES bit is set to “1”, the SYNC port will follow
whatever value is written to this bit. If this mechanism is
used to control the SYNC port it is up to software to
ensure that the signal is high long enough to meet the
specification of the external device.
This bit has priority over the TIMEDSYNC bit.
If this bit is set to “1”, the SYNC port is forced to “1” for five
pulses of the 2.9491 MHz (0.339 µs x 5 = 1.695 µs
maximum SYNC pulse and 1.356 µs minimum SYNC
pulse using this clock). After which this bit is zeroed,
allowing the SYNC to be controlled via the BITCLK
counter.
24
8
23
7
22
6
21
5
20
4
19
3
EFORCES
EP93xx User’s Guide
18
2
AC’97 Controller
FORCED
SYNC
17
1
TIMED
SYNC
22-23
16
0
22
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