EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 133

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and
PCLK<=50 MHz and FCLK >= HCLK > PCLK. Refer to register,
the detailed configuration information regarding the divider bit fields.
MAX = 100 MHz
External Clock
PCLK Divide = 1, 2, 4, 8
HCLK
Div
PCLK
Div
Figure 5-3. Bus Clock Generation
Copyright 2007 Cirrus Logic
PLL1
FCLK
Div
MAX = 500 MHz
MAX = 250 MHz
MAX = 50 MHz
For 2nd stage dividers:
HCLK Divide = 1, 2, 4, 5, 6,
FCLK Divide = 1, 2, 4, 8, 16
8, 16, 32
“ClkSet1” on page
FCLK
HCLK
PCLK
EP93xx User’s Guide
System Controller
5-18, for
5-7
5