EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 533

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
14.4.3 HDLC Transmit
14.4.4 HDLC Receive
In normal operation, the HDLC transmitter either continuously sends flags or holds the
transmit pin in a marking state, depending on the setting of the UART1HDLCCtrl.IDLE bit.
When data appears in the transmit FIFO, it begins sending a packet. If in the marking state, it
sends from 1 to 16 opening flags, as specified by the UART1HDLCCtrl.FLAG field. If already
sending flags, it ensures that at least the specified number have been sent. It then begins
sending the bytes in the FIFO, inserting and modifying the data depending on the HDLC
mode.
In asynchronous HDLC, the transmitter enforces control-octet transparency. Whenever a flag
byte (01111110b) or an escape byte (01111101b) appears in the data, the transmitter inverts
the fifth bit and precedes it with an escape byte.
In synchronous HDLC, the transmitter performs bit-stuffing (except for flags). Whenever five
consecutive “1” bits appear in the transmitted bit stream, a “0” bit is inserted, preventing six
ones from appearing consecutively.
When the transmit FIFO under-runs, the HDLC transmitter does one of two things (depending
on the setting of the UART1HDLCCtrl.TUS bit). If the TUS bit is zero, the transmitter first
sends the CRC (if CRC is enabled) and then sends from 1 to 16 closing flags, as specified in
the UART1HDLCCtrl.FLAG field, terminating the packet.
If TUS is one, the transmitter aborts the packet. In synchronous HDLC, it sends a byte of all
ones (since seven consecutive ones signifies an abort), following by at least one closing flag.
In asynchronous HDLC, it sends an escape and then at least one closing flag. The number of
closing flags is from 1 to 16, as specified in the UART1HDLCCtrl.FLAG field.
When a packet ends, the UART1HDLCSts.TFC bit is set, and if UART1HDLCCtrl.TFCEN is
set, an interrupt is generated. When a packet is aborted, the UART1HDLCCtrl.TAB bit is set,
also generating an interrupt if UART1HDLCCtrl.TABEN is set.
The HDLC receiver continuously reads bytes from the UART receiver until it finds a flag
followed by a byte other than a flag. Then, if in asynchronous mode, it processes the
incoming bytes (including the first after the flag), reversing control-octet transparency, or, if in
synchronous mode, it reverses bit-stuffing. Processed bytes are placed in the receive FIFO.
When programmed to receive a Manchester encoded bit stream, UART1HDLCSts.PLLCS
indicates whether the DPLL in the receiver has locked on to the carrier.
CMAS TXCM RXCM TXENC RXENC SYNC
1
1
-
1
1
1
UART1HDLCCtrl Bits Set
Table 14-2. Legal HDLC Mode Configurations (Continued)
1
1
-
-
-
-
Copyright 2007 Cirrus Logic
1
-
-
1
1
1
Transmit Mode
External clock
Internal clock
Internal clock
UART1 With HDLC and Modem Control Signals
Receive Mode
External clock
Internal clock
Manchester
EP93xx User’s Guide
14-11
14