EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 200

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

7
7-18
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.8.8 GrySclLUT Timing Diagram
Where FRAME[1:0] = FRAME_CNT3 or FRAME_CNT4 as defined by FRAME at address
Pixel_In,
VCNT[1:0] = VERT_CNT3 or VERT_CNT4 as defined by VERT at address Pixel_In, and
HCNT[1:0] = HORZ_CNT3 or HORZ_CNT4 as defined by HORZ at address Pixel_In.
This is the GrySclLUT table in an easily readable form. To understand how to use this table
and to know how to fill the table with correct values requires a good understanding on how
the table is used by the grayscale logic.
Table 7-5
clock for the display. This clock controls which pixel is being accessed as the image is being
rasterized on the display.
Assume that the first 8 registers have the HCNT, VCNT and FRAME counter registers set up
for 4 counts. The last column shows which register is used to retrieve the look up value and
the bit position within that register that is used as the source to send to the COLORMUX for
the given clock.
Clocks 4, 9, 14, and 19 represent all remaining pixels on the line. Clocks 24 and 29 represent
all remaining pixels for the frame. These entries will keep this example table to a manageable
size.
The FRAME count and PIXEL value are used to indicate which register contains the data.
HCNT and VCNT are used to indicate which bit in the identified register is to be used for the
given grayscale value.
shows the timing diagram. The clock column represents a free running master
Clock
Clock
10
12
13
14
15
16
17
11
0
1
2
3
4
5
6
7
8
9
HCNT
HCNT
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
“
“
“
VCNT
VCNT
Copyright 2007 Cirrus Logic
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
“
“
“
Table 7-5. Grayscale Timing Diagram
FRAME
FRAME
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
“
“
“
PIXEL
PIXEL
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
“
“
“
Register Address / Value
Register Address / Value
(base + 94) / D10
(base + 94) / D12
(base + 94) / D13
(base + 94) / D14
(base + 94) / D11
(base + 94) / D0
(base + 94) / D1
(base + 94) / D2
(base + 94) / D3
(base + 94) / D4
(base + 94) / D5
(base + 94) / D6
(base + 94) / D7
(base + 94) / D8
(base + 94) / D9
DS785UM1