EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 157

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

I2SClkDiv
DS785UM1
MENA
SENA
31
15
Address:
Default:
Definition:
Bit Descriptions:
SLAVE
ESEL
30
14
ORIDE
PSEL
29
13
28
12
0x8093_008C - Read/Write, Software locked
0x0000_0000
Configures the I
RSVD:
SENA:
SLAVE:
ORIDE:
DROP:
SPOL:
LRDIV:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
2
S block audio clocks MCLK, SCLK, and LRCLK.
25
9
Reserved. Unknown During Read.
Enable audio clock generation.
I
slave. SCLK and LRCLK are chip inputs. The clock
configuration controls in this register are ignored in slave
mode.
Override I
1 - Override the SAI_MSTR_CLK_CFG from the I
and use the I2SClkDiv Register settings.
0 - Use the I2S SAI_MSTR_CLK_CFG signals.
Drop SCLK clocks.
1 - When in 64x mode, drop 8 SCLKs.
0 - Do not drop SCLKs.
SCLK polarity. Defines the SCLK edge that aligns to
LRCLK transitions.
1 - LRCLK transitions on the falling SCLK edge.
0 - LRCLK transitions on the rising SCLK edge.
LRCLK divide select.
00 - LRCK = SCLK / 32
01 - LRCK = SCLK / 64
10 - LRCK = SCLK / 128
11 - Reserved
2
RSVD
PDIV
S slave. Configures the I
24
8
2
RSVD
S master configuration.
23
7
22
6
21
5
2
S clock system to operate as a
DROP
20
4
SPOL
MDIV
19
3
EP93xx User’s Guide
System Controller
18
2
LRDIV
17
1
2
S block
SDIV
16
5-31
0
5