EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 421
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
DS785UM1
Current State:
NextBuffer:
Copyright 2007 Cirrus Logic
Indicates the state that the Channel FSM is currently in:
00 - IDLE
01 - STALL
10 - ON
11 - NEXT
Informs the NFB service routine, after a NFB interrupt,
which pair of BASEx/MAXCOUNTx registers is free for
update.
0 - Update MAXCNT0/BASE0
1 - Update MAXCNT1/BASE1
The NextBuffer bit gets set to “1” when a write occurs to
BASE0 and it gets set to “0” when a write occurs to
BASE1. This bit alone cannot be used to determine which
of the two buffers is currently being transferred to. For
example, if BASE0 is written to, then NextBuffer gets set
to “1” and transfers will occur using buffer0. If, during this
transfer BASE1 gets written to, then NextBuffer gets set to
“0”, but the current transfer will continue using buffer0 until
it terminates. Then the DMA switches over to using
buffer1, at which time the NFB interrupt is generated and
software reads the NextBuffer status bit to determine what
buffer descriptor is now free for update. In this case it is
buffer0.
The NextBuffer status bit can be used in conjunction with
the CurrentState status bits to determine the active buffer.
If CurrentState = DMA_ON and NextBuffer = 1 then
Buffer0 is the active buffer.
If CurrentState = DMA_ON and NextBuffer = 0 then
Buffer1 is the active buffer.
If CurrentState = DMA_NEXT and NextBuffer = 0 then
Buffer0 is the active buffer.
If CurrentState = DMA_NEXT and NextBuffer =1 then
Buffer1 is the active buffer.
EP93xx User’s Guide
DMA Controller
10-27
10
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