EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 413

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors
10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors
10.1.12.3 M2M Channel Buffer Descriptors
10.1.13 Bus Arbitration
Only one Rx buffer descriptor is allocated per transaction. There are five Rx buffer
descriptors, one for each of the five receive channels. Each buffer descriptor allows a
channel double buffering scheme by containing programming for two buffers, that is, two
system buffer base addresses and two buffer byte counts. This ensures that there is always
one free buffer available for transfers to avoid potential data over/under-flow due to software-
introduced latency.
Only one Tx buffer descriptor is allocated per transaction. There are five Tx buffer
descriptors, one for each of the five transmit channels Each buffer descriptor allows a
channel double buffering scheme by containing programming for two buffers, that is, two
system buffer base addresses and two buffer byte counts. This ensures that there is always
one free buffer available for transfers to avoid potential data over/under-flow due to software
introduced latency.
Only one M2M channel buffer descriptor is allocated per transaction. There are two M2M
buffer descriptors, one for each of the 2 M2M channels. Each buffer descriptor allows a
channel double buffering scheme by containing programming for two buffers, that is, two
source base addresses, two destination base addresses and two buffer byte counts. The
buffers are limited to 64 kBytes (0xFFF). This ensures that there is always one free buffer
available for transfers which avoids potential data overflow/underflow due to software
introduced latency.
When ready to do a transfer, the DMA Controller arbitrates internally between DMA
Channels, then requests AHB bus access to the external AHB bus arbiter. Then a default
setting of M2P having a higher priority than M2M is implemented. The default setting is
programmable and can be changed if required (DMA Arbitration register bit[0] = CHARB).
The channel arbitration scheme is based on rotating priority, the order is as shown below in
Table
10-2:
Highest
Table 10-2. M2P DMA Bus Arbitration
Copyright 2007 Cirrus Logic
Internal Arbitration Priority
CHARB = 0
M2P Ch 0
M2P Ch 1
M2P Ch 2
M2P Ch 3
M2P Ch 4
M2P Ch 5
M2P Ch 6
CHARB = 1
M2M Ch 0
M2M Ch 1
M2P Ch 0
M2P Ch 1
M2P Ch 2
M2P Ch 3
M2P Ch 4
EP93xx User’s Guide
DMA Controller
10-19
10