EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 593

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

UART3HDLCRXInfoBuf
DS785UM1
RSVD
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808E_0218 - Read/Write
0x0000_0000
HDLC Receive Information Buffer Register. This register is loaded when the
last data byte in a received frame is read from the receive FIFO. The CPU has
until the end of the next frame to read this register, or the RIL bit in the HDLC
Status Register will be set.
RSVD:
BC:
BFRE:
BROR:
BCRE:
BRAB:
27
11
26
10
Copyright 2007 Cirrus Logic
BC
25
9
Reserved. Unknown During Read.
Received frame Byte Count.
The total number of valid bytes read from the RX FIFO
during the last HDLC frame.
Buffered Framing Error.
0 - No framing errors were encountered in the last frame.
1 - A framing error occurred during the last frame, causing
the remainder of the frame to be discarded.
Buffered Receiver Over Run.
0 - The RX buffer did not overrun during the last frame.
1 - The receive FIFO did overrun during the last frame.
The remainder of the frame was discarded.
Buffered CRC Error.
0 - No CRC check errors occurred in the last frame.
1 - The CRC calculated on the incoming data did not
match the CRC value contained in the last frame.
Buffered Receiver Abort.
0 - No abort occurred in the last frame.
1 - The last frame was aborted.
24
8
RSVD
23
7
22
6
21
5
20
4
UART3 With HDLC Encoder
BFRE
19
3
EP93xx User’s Guide
BROR
18
2
BCRE
17
1
BRAB
16-17
16
0
16