EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 144
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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Manufacturer
Quantity
Price
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5
STFClr
ClkSet1
5-18
System Controller
EP93xx User’s Guide
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
Note: When a write is performed to the ClkSet1 location, it must be immediately followed by 5
Note: The value in the register is the actual coefficient minus one.
30
14
30
14
RSVD
PLL1 X1FBD1
29
13
29
13
NOP instructions. This is needed to flush the instruction pipeline in the ARM920T core.
Writing to this register will cause the the device to enter Standby for between 8 ms to
16 ms. Reading from this register will not cause an entry into Standby mode.
28
12
28
12
0x8093_001C - Write
Writing to the STFClr location will clear the CLDFLG, WDTFLG and RSTFLG
in the register,
the clearing.
RSVD:
0x8093_0020 - Read/Write
The ClkSet1 system control register is one of two register that control clock
speeds.
RSVD:
PLL1_X2IPD:
27
27
11
11
FCLK DIV
26
10
26
10
“PwrSts” on page
Copyright 2007 Cirrus Logic
25
25
9
9
There are no readable bits in this register.
Reserved. Unknown During Read.
These 5 register bits set the input divider for PLL1
operation. On power-on-reset the value is set to 00111b (7
decimal).
SMC ROM
24
8
PLL1 X2FBD2
24
8
RSVD
RSVD
23
nBYP1
7
23
7
5-14. Any data written to the register triggers
22
6
22
6
HCLK DIV
21
5
21
5
20
4
20
4
19
3
19
3
PCLK DIV
PLL1 X2IPD
18
2
18
2
17
1
17
DS785UM1
1
PLL1_PS
16
0
16
0
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