EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 40

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

2
2-2
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.2.2 Block Diagram
2.2.3 Operations
The ARM920T core follows a Harvard architecture and consists of an ARM9TDMI core,
MMU, instruction and data cache. The core supports both the 32-bit ARM and 16-bit Thumb
instruction sets.
The internal bus structure (AMBA) includes both a high speed and low speed bus. The high
speed bus AHB (Advanced High-performance Bus) contains a high speed internal bus clock
to synchronize co-processor, MMU, cache, DMA controller, and memory modules. AMBA
includes a AHB/APB bridge to the lower speed APB (Advanced Peripheral Bus). The APB
bus connects to lower speed peripheral devices such as UARTs and GPIOs.
The MMU provides memory address translation for all memory and peripherals designed to
remap memory devices and peripheral address locations. Sections, large, small and tiny
pages are programmable to map memory in 1 Mbyte, 64 kbyte, 4 kbyte, 1 kbyte size blocks.
To increase system performance, a 64-entry translation look-aside buffer will cache 64
address locations before a TLB miss occurs.
Interface
External
Co-Proc
JTAG
Data cache
R13
Processor core
EmbeddedICE)
ARM9TDMI
(Integral
Instruction
R13
cache
Figure 2-1. ARM920T Block Diagram
Copyright 2007 Cirrus Logic
Data MMU
Instruction
MMU
CP15
Write Back
PA TAG
RAM
Buffer
Write
AMBA
Bus
Int.
APB
DS785UM1