EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 652

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

20
20.1 Registers
Register Descriptions
RTCData
20-4
Real Time Clock With Software Trim
EP93xx User’s Guide
20.1.2 Reset Control
31
15
Address:
Default:
Definition:
Bit Descriptions:
The RTC block level reset operation is a bit complicated. The reset strategy is for the time-
keeping part of the RTC to survive a system reset, and only be initialized by a power-on reset.
The RTC interrupt enable is cleared by a user reset, so that a time count match (alarm
interrupt) would disable with system reset.
The following register is initialized only by PRSTn: RTCSWComp
The following registers are initialized by PRSTn: RTCData, RTCMatch, RTCLoad, and
RTCCtrl.
30
14
29
13
0x8092_000C
0x8092_0000
0x8092_0004
0x8092_0008
0x8092_0010
0x8092_0098
Address
28
12
0x8092_0000 - Read Only
0x0000_0000
RTC Data Register. Contains the 32 bit RTC counter value. This counter is
incremented by the 1 Hz clock output from the RTC Trim module.
RTCDR:
27
11
Table 20-1. Real Time Clock Register Memory Map
26
10
"RTCSWComp"
Copyright 2007 Cirrus Logic
"RTCMatch"
"RTCLoad"
"RTCData"
"RTCCtrl"
"RTCSts"
25
Name
9
Counter value.
24
8
RTCDR
RTCDR
23
7
RTC Data Register
RTC Match Register
RTC Status/EOI Register
RTC Load Register
RTC Control Register
RTC Software Compensation
22
6
21
5
Description
20
4
19
3
18
2
17
1
DS785UM1
16
0