PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 88

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
REGISTER 7-1:
DS39616B-page 86
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated
0 = The write operation completed normally
WREN: Erase/Write Enable bit
1 = Allows erase/write cycles
0 = Inhibits erase/write cycles
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
0 = Write cycle is completed
RD: Read Control bit
1 = Initiates a memory read
0 = Read completed
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
EEPGD
R/W-x
Note:
(cleared by completion of erase operation)
(MCLR or WDT Reset during self-timed erase or program operation)
cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows trac-
ing of the error condition.
R/W-x
CFGS
S = Settable only
- n = Value at POR
U-0
Preliminary
—
R/W-0
FREE
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
WREN
R/W-0
 2003 Microchip Technology Inc.
‘0’ = Bit is cleared
R/S-0
WR
R/S-0
RD
bit 0