PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 166

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
FIGURE 16-4:
DS39616B-page 164
Note 1: TMR5 is a synchronous time base input to the Input Capture, prescaler = 1:1. It increments on Q1 rising edge.
TMR5
CAP1 pin
CAP1BUF
TMR5 reset
Instruction
Execution
Note 1: Input
2: IC1 is configured in Edge Capture mode (CAP1M3:CAP1M0 = 0010) with the time base reset upon edge capture
3: TMR5 value is latched by CAP1BUF on T
4: TMR5 Reset is normally an asynchronous reset signal to TMR5. When used with the input capture, it is active immedi-
5: TMR5 Reset pulse is disabled by clearing CAP1REN bit (e.g, BCF CAP1CON, CAP1REN).
(1)
2: When the Input Capture mode is changed
3: During IC mode changes, the prescaler
(2)
(CAP1REN = 1) and no noise filter.
the write will always take precedence. All input capture buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated with
the incremented value of the time base on the next T
when Reset occurs).
ately after the time base value is captured.
(3)
(cleared) when the Input Capture module
is disabled (CAPxM = 0000).
without first disabling the module and
entering the new Input Capture mode, a
false interrupt (or special event trigger on
IC1) may be generated. The user should
either (1) disable the Input Capture before
entering another mode or (2) disable IC
interrupts to avoid false interrupts during
IC mode changes.
count will not be cleared, therefore the
first capture in the new IC mode may be
from the non-zero prescaler.
MOVWF CAP1CON
(4)
OSC
capture
EDGE CAPTURE MODE TIMING
Q1Q2 Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4
0012
prescalers
0013
are
0014
reset
CY
ABCD
Preliminary
. In the event that a write to TMR5 coincides with an input capture event,
0015
CY
clock edge when the capture event takes place (see Note 4
0016
0000
16.1.1
In this mode, the value of the time base is captured
either on every rising edge, every falling edge, every
4th rising edge, or every 16th rising edge. The edge
present on the input capture pin (CAP1, CAP2 or
CAP3) is sampled by the synchronizing latch. The
signal is used to load the input capture buffer (ICxBUF
register) on the following Q1 clock (see Figure 16-4).
Consequently, Timer5 is either reset to ‘0’ (Q1
immediately following the capture event) or left free
running, depending on the setting of Capture Reset
Enable, CAPxREN, in the CAPxCON register.
Note:
BCF CAP1CON, CAP1REN
0001
EDGE CAPTURE MODE
On the first capture edge following the
setting of the Input Capture mode (i.e.,
MOVWF CAP1CON), Timer5 contents are
always captured into the corresponding
input capture buffer (i.e., CAPxBUF).
Timer5 can optionally be reset; however,
this is dependent on the setting of the
Capture Reset Enable bit (CAPxREN),
see Figure 16-4.
0002
 2003 Microchip Technology Inc.
0003
0000
0001
0002
0002
Note 5