PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 47

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The PIC18F2331/2431/4331/4431 devices differenti-
ate between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
FIGURE 4-1:
 2003 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: This is the INTRC source from the internal oscillator block, and is separate from the RC oscillator of the CLKI pin.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: See Table 4-1 for time-out situations.
Instruction
INTRC
RESET
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
V
(1)
Detect
Sleep
DD
WDT
Reset
Rise
OST
PWRT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
POR Pulse
BOREN
1024 Cycles
65.5 ms
PIC18F2331/2431/4331/4431
Preliminary
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-2.
These bits are used in software to determine the nature
of the Reset. See Table 4-3 for a full description of the
Reset states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
The MCLR input provided by the MCLR pin can be dis-
abled with the MCLRE bit in Configuration Register 3H
(CONFIG3H<7>). See Section 22.1 “Configuration
Bits” for more information.
S
R
DS39616B-page 45
Q
Enable OST
Enable PWRT
Chip_Reset
(2)