PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 200

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
17.6.5
The Complementary mode of PWM operation is useful
to drive one or more power switches in half-bridge
configuration as shown in Figure 17-16. This inverter
topology is typical for a 3-phase induction motor,
brushless DC motor or a 3-phase Uninterruptible
Power Supply (UPS) control applications. Each
upper/lower
complementary PWM signal. Dead time may be
optionally inserted during device switching where both
outputs are inactive for a short period (see
Section 17.7
Complementary mode, the duty cycle comparison units
are assigned to the PWM outputs as follows:
• PDC0 register controls PWM1/PWM0 outputs
• PDC1 register controls PWM3/PWM2 outputs
• PDC2 register controls PWM5/PWM4 outputs
• PDC3 register controls PWM7/PWM6 outputs
PWM1/3/5/7 are the main PWMs that are controlled by
the
complemented outputs. When using the PWMs to
control the half bridge, the odd number PWMs can be
used to control the upper power switch and the even
numbered PWMs for the lower switches.
DS39616B-page 198
PDC
COMPLEMENTARY PWM
OPERATION
registers
power
“Dead
switch
and
Time
PWM0/2/4/6
pair
Generators”).
is
fed
are
by
Preliminary
the
In
a
FIGURE 17-16:
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in
the PWMCON0 register. The PWM I/O pins are set to
Complementary mode by default upon all kinds of
device resets.
+V
TYPICAL LOAD FOR
COMPLEMENTARY PWM
OUTPUTS
 2003 Microchip Technology Inc.
3 Phase
Load