PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 156

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
15.4
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against the TMR1
register pair value. When a match occurs, the RC2/
CCP1 (RC1/CCP2) pin:
• Is driven High
• Is driven Low
• Toggles output (High-to-Low or Low-to-High)
• Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
15.4.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
FIGURE 15-2:
DS39616B-page 154
Note:
Special Event Trigger will:
Compare Mode
Reset Timer1, but not set Timer1 interrupt flag bit,
and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion (CCP2 only)
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
RC2/CCP1 pin
RC1/CCP2 pin
Output Enable
Output Enable
TRISC<2>
TRISC<1>
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
Q
R
R
S
S
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
Mode Select
Mode Select
Output
Output
Logic
Logic
Preliminary
Set Flag bit CCP1IF
Set Flag bit CCP2IF
Match
Match
15.4.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
15.4.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
15.4.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair. Additionally, the CCP2 special event
trigger will start an A/D conversion if the A/D module is
enabled.
Note:
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP2
module will not set the Timer1 interrupt
flag bit.
 2003 Microchip Technology Inc.
CCPR1H CCPR1L
CCPR2H CCPR2L
TMR1H
Comparator
Comparator
TMR1L