PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 31

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.8
When the device executes a SLEEP instruction, the
system is switched to one of the power-managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power-Managed Modes” for details.
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock, and may be enabled to
support various special features, regardless of the
power-managed mode (see Sections 22.2 through
directly to clock the system, or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real-
time clock. Other features may be operating that do not
require a system clock source (i.e., SSP slave, PSP,
INTn pins, A/D conversions and others).
TABLE 2-3:
 2003 Microchip Technology Inc.
22.4). The INTOSC output at 8 MHz may be used
RC, INTIO1
RCIO, INTIO2
ECIO
EC
LP, XT, and HS
Note:
secondary
Effects of Power-Managed Modes
on the Various Clock Sources
See Table 4-1 in the Section 4.0 “Reset”, for time-outs due to Sleep and MCLR Reset.
OSC Mode
clock
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
modes
(SEC_RUN
Floating, external resistor
should pull high
Floating, external resistor
should pull high
Floating, pulled by external clock
Floating, pulled by external clock
Feedback inverter disabled, at
quiescent voltage level
PIC18F2331/2431/4331/4431
and
Preliminary
OSC1 Pin
2.9
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset until the device power supply is stable under
normal circumstances, and the primary clock is
operating and stable. For additional information on
power-up delays, see Sections 4.1 through 4.5.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 25-8), if enabled, in Configuration register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the crys-
tal oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of 5 to 10 s following POR, while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only delay that occurs when any of the EC,
RC or INTIO modes are used as the primary clock
source.
Power-up Delays
Configured as PORTA, bit 6
At logic low (clock/4 output)
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled, at
quiescent voltage level
OSC2 Pin
DS39616B-page 29