PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 163

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.1
The Input Capture (IC) submodule implements the
following features:
• Three channels of independent input capture
• Edge-trigger, period or pulse width measurement
• Programmable prescaler on every input capture
• Special event trigger output (IC1 only)
• Selectable noise filters on each capture input
FIGURE 16-2:
 2003 Microchip Technology Inc.
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
operating modes for each channel
channel
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
velcap
CAP1 Pin
(2)
Input Capture
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
FLTCK<2:0>
VELM
Noise
Filter
1
0
MUX
3
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
Prescaler
CAP1M<3:0>
1, 4, 16
Q Clocks
Clock/
Reset/
Interrupt
Decode
Logic
4
Select
Mode
and
Q clocks
CAP1M<3:0>
PIC18F2331/2431/4331/4431
Preliminary
First Event
Reset
CAP1BUF_clk
Input channel (IC1) includes a special event trigger
that can be configured for use in Velocity Measure-
ment mode. Its block diagram is shown in Figure 16-2.
IC2 and IC3 are similar, but lack the special event trig-
ger features or additional velocity-measurement logic.
A
Figure 16-3. Please note that the time base is Timer5.
Special
Event
Reset
IC1_TR
IC1IF
representative
Timer5 Logic
block
CAP1BUF/VELR
diagram
TMR5
Timer
Reset
Control
DS39616B-page 161
Reset
Control
(1)
Timer5 Reset
is
Clock
shown
Reset
in