PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 73

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.12
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 5-9.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 5-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 5-5:
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required:
1.
2.
3.
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
 2003 Microchip Technology Inc.
NEXT
CONTINUE
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
data
Indirect Addressing, INDF and
FSR Registers
LFSR
CLRF
BTFSS
GOTO
from
FSR0, 0x100 ;
POSTINC0
FSR0H, 1
NEXT
the
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
address
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
pointed
PIC18F2331/2431/4331/4431
to
Preliminary
by
If INDF0, INDF1 or INDF2 are read indirectly via a FSR,
all ‘0’s are read (zero bit is set). Similarly, if INDF0,
INDF1 or INDF2 are written to indirectly, the operation
will be equivalent to a NOP instruction and the Status
bits are not affected.
5.12.1
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation using one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
• Do nothing to FSRn after an indirect access (no
• Auto-decrement FSRn after an indirect access
• Auto-increment FSRn after an indirect access
• Auto-increment FSRn before an indirect access
• Use the value in the WREG register as an offset
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the Status
register. For example, if the indirect address causes the
FSR to equal ‘0’, the Z bit will not be set.
Auto-incrementing or auto-decrementing a FSR affects
all 12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed. The
WREG offset range is -128 to +127.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing write is performed when the
target address is an FSRnH or FSRnL register, the data
is written to the FSR register, but no pre- or post-
increment/decrement is performed.
change) – INDFn
(post-decrement) – POSTDECn
(post-increment) – POSTINCn
(pre-increment) – PREINCn
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
INDIRECT ADDRESSING
OPERATION
DS39616B-page 71