PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 126

IC MCU FLASH 8KX16 44TQFP

PIC18F4431-E/PT

Manufacturer Part Number
PIC18F4431-E/PT
Description
IC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4431-E/PT

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4431-E/PT
Manufacturer:
JOHANSON
Quantity:
24 000
Part Number:
PIC18F4431-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F2331/2431/4331/4431
10.4
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
FIGURE 10-21:
DS39616B-page 124
Note:
Note:
PORT/PWM Select
PWM6,7 Data Out
PORTD, TRISD and LATD
Registers
PORTD is only available on PIC18F4X31
devices.
On a Power-on Reset, these pins are
configured as digital inputs.
RD PORTD
WR TRISD
WR LATD
Data Bus
PORTD
or
BLOCK DIAGRAM OF RD7:RD6 PINS
TRIS Latch
Data Latch
D
D
RD TRISD
CK
CK
RD LATD
Q
Q
Q
Q
Preliminary
0
1
Q
PORTD includes PWM<7:6> complementary fourth
channel PWM outputs. PWM4 is the complementary
output of PWM5 (the third channel), which is multi-
plexed with the RB5 pin. This output can be used as the
alternate output using the PWM4MX configuration bit in
CONFIG3L when the low-voltage programming pin
(PGM) is used on RB5.
RD1, RD2 and RD3 can be used as the alternate out-
put for SDO, SDI/SDA and SCK/SCL using the SSPMX
configuration bit in CONFIG3L.
RD4 an be used as the alternate output for FLTA using
the FLTAMX configuration bit in CONFIG3L.
EXAMPLE 10-4:
CLRF
CLRF
MOVLW
MOVWF
EN
D
PORTD
LATD
0xCF
TRISD
V
V
N
P
SS
DD
Schmitt
Trigger
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
INITIALIZING PORTD
 2003 Microchip Technology Inc.
RD[7:6] Pin

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