PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 95

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTA<4>). In addition, enable bit SPEN
(RCSTA<7>) is set in order to configure the
RC4/C2OUT/TX/CK and RC5/RX/DT I/O pins to CK
(clock) and DT (data) lines, respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCTL<5>); setting
SCKP sets the IDLE state on CK as high, while clearing
the bit, sets the IDLE state low. This option is provided
to support Microwire
10.4.1
The USART transmitter block diagram is shown in
Figure 10-2. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
FIGURE 10-10:
 2004 Microchip Technology Inc.
RC4/C2OUT/
TX/CK pin
(SCKP = 0)
RC4/C2OUT/
TX/CK pin
(SCKP = 1)
TRMT bit
RC5/RX/
DT pin
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
USART Synchronous Master
Mode
‘1’
USART SYNCHRONOUS MASTER
TRANSMISSION
Write Word 1
®
devices with this module.
SYNCHRONOUS TRANSMISSION
bit 0
Write Word 2
bit 1
Word 1
bit 2
Preliminary
Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Once the TXREG register transfers the data to the TSR
register (occurs in one T
and interrupt bit TXIF (PIR1<4>) is set. The interrupt
can be enabled/disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of
the state of enable bit TXIE, and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit,
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR register is empty. The TSR is
not mapped in data memory, so it is not available to the
user.
To set up a Synchronous Master Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
bit 7
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
bit 0
Word 2
bit 1
CYCLE
PIC16F688
), the TXREG is empty
DS41203B-page 93
bit 7
‘1’