PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 88

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
10.3
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
USART uses standard non-return-to-zero (NRZ) format
(one Start bit, eight or nine data bits and one Stop bit).
The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit baud rate generator can be used
to derive standard baud rate frequencies from the
oscillator.
The USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally inde-
pendent, but use the same data format and baud rate.
The baud rate generator produces a clock, either x16
or x64 of the bit shift rate, depending on the BRGH and
BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity is
not supported by the hardware, but can be
implemented in software and stored as the 9th data bit.
Asynchronous mode is available in all times. It is avail-
able in Sleep mode only when auto-wake-up on Sync
Break is enabled. The baud rate generator values may
need to be adjusted if the clocks are changed.
When operating in Asynchronous mode, the USART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-wake-up on Sync Break Character
• 13-bit Break Character Transmit
• Auto Baud Rate Detection
DS41203B-page 86
USART Asynchronous Mode
Preliminary
10.3.1
The USART transmitter block diagram is shown in
Figure 10-2. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one
empty and flag bit TXIF (PIR1<4>) is set. This interrupt
can be enabled/disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of
the state of enable bit TXIE and cannot be cleared in
software. Flag bit TXIF is not cleared immediately upon
loading the transmit buffer register TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following
a load of TXREG will return invalid results.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. Status bit TRMT is a read
only bit, which is set when the TSR register is empty.
No interrupt logic is tied to this bit, so the user has to
poll this bit in order to determine if the TSR register is
empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
Note 1: The TSR register is not mapped in data
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
2: Flag bit TXIF is set when enable bit TXEN
USART ASYNCHRONOUS
TRANSMITTER
memory, so it is not available to the user.
is set.
 2004 Microchip Technology Inc.
T
CY
), the TXREG register is