PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 92

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
FIGURE 10-6:
TABLE 10-6:
DS41203B-page 90
Legend:
Addr
0Ch
8Ch
12h
13h
14h
15h
16h
17h
11h
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
PIR1
BAUDCTL ABDOVF
SPBRGH USART Baud Rate High Generator
SPBRG
RCREG
TXREG
TXSTA
RCSTA
PIE1
RCIDL
Name
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
CSRC
SPEN
EEIF
EEIE
Bit 7
Start
ASYNCHRONOUS RECEPTION
bit
bit 0
RCIDL
ADIE
ADIF
Bit 6
RX9
TX9
bit 1
TXEN
SREN
RCIE
RCIF
Bit 5
—
bit 7/8
SYNC
CREN
SCKP
Bit 4
C2IF
C2IE
Preliminary
Stop
bit
Word 1
RCREG
SENDB
ADDEN
BRG16
Bit 3
C1IF
C1IE
Start
bit
bit 0
OSFIF
OSFIE
BRGH
FERR
Bit 2
—
OERR
TRMT
WUE
TXIE
Bit 1
TXIF
bit 7/8 Stop
Word 2
RCREG
bit
TMR1IF
TMR1IE
ABDEN
RX9D
TX9D
Bit 0
Start
 2004 Microchip Technology Inc.
bit
0000 0000
00-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000X
0000 0000
POR, BOD
Value on
bit 7/8
Stop
0000 0000
00-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000X
0000 0000
bit
Value on
all other
Resets