D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 783

• Manufacturer Part Number: D6417709SHF200BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SHF200BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table A.10 Pin States (PCMCIA/Big Endian)
CS6 to CS2, CS0
RD
RD/WR
BS
RAS3U/PTE[2]
RAS3L/PTJ[0]
CASL/PTJ[2]
CASU/PTJ[3]
WE0/DQMLL
WE1/DQMLU/WE
WE2/DQMUL/
ICIORD/PTK[6]
WE3/DQMUU/
ICIOWR/PTK[7]
CE2A/PTE[4]
CE2B/PTE[5]
CKE/PTK[5]
WAIT
IOIS16/PTG[7]
A25 to A0
D7 to D0
D15 to D8
D31 to D16
Pin
W High
W Low
W High
W Low
W High
W High
R Low
R High
R High
R High
R High
R High
Enabled
Enabled
High
High
High
High
High
High
Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Enabled
Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Address
Valid
data
High-Z
High-Z
8-Bit Bus
Access
Word/
Width
Long-
Byte/
word
PCMCIA Memory Interface (Area 5)
* 2
* 2
* 1
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
Low
High
High
High
High
High
High
Enabled
Address
Invalid
data
Valid data Invalid
High-Z
Access
dress
Byte
(Ad-
2n)
* 2
16-Bit Bus Width
* 1
High
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
Low
High
High
High
High
Low
High
Enabled
Address
Valid
data
data
High-Z
Access
2n + 1)
dress
Byte
(Ad-
* 2
* 1
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
Low
High
High
High
High
Low
High
Enabled
Address
Valid
data
Valid
data
High-Z
Access
Word/
Long-
word
* 2
* 1
Enabled
High
High
High
Low
Enabled
High
High
High
High
High
High
High
High
Low
High
High
Low
High
High
Enabled
Address
Valid
data
High-Z
High-Z
8-Bit Bus
Access
Width
Word/
Long-
Byte/
word
Rev. 5.00, 09/03, page 737 of 760
PCMCIA I/O Interface (Area 5)
* 2
* 2
* 1
Enabled
High
High
High
Low
Enabled
High
High
High
High
High
High
High
High
Low
High
High
Low
High
High
Enabled
Address
Invalid
data
Valid
data
High-Z
Access
dress
Byte
(Ad-
2n)
* 2
16-Bit Bus Width
* 1
High
High
High
High
Low
Enabled
High
High
High
High
High
High
High
High
Low
High
High
Low
Low
High
Enabled
Address
Valid
data
Invalid
data
High-Z
Access
2n + 1)
dress
Byte
(Ad-
* 2
* 1
Enabled
High
High
High
Low
Enabled
High
High
High
High
High
High
High
High
Low
High
High
Low
Low
High
Enabled
Address
Valid
data
Valid
data
High-Z
Access
Word/
Long-
word
* 2
* 1