D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 136

IC SUPER H MPU ROMLESS 208LQFP

D6417709SHF200BV

Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417709SHF200BV

Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers either to the next instruction after a delayed unconditional branch instruction or to
the next instruction when a delayed conditional branch instruction is true.
4.2.4
Table 4.3 lists the exception codes written to the EXPEVT register (for reset or general
exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to identify
each specific exception event.
Table 4.3
Exception Type
Reset
General exception events
General interrupt requests
Rev. 5.00, 09/03, page 90 of 760
Exception Codes
Exception Codes
Exception Event
Power-on reset
Manual reset
UDI reset
TLB miss/invalid (read)
TLB miss/invalid (write)
Initial page write
TLB protection violation (read)
TLB protection violation (write)
CPU address error (read)
CPU address error (write)
Unconditional trap (TRAPA instruction)
Illegal general instruction exception
Illegal slot instruction exception
User breakpoint trap
DMA address error
Nonmaskable interrupt
UDI interrupt
External hardware interrupts:
IRL3–IRL0 = 0000
IRL3–IRL0 = 0001
Exception Code
H'000
H'020
H'000
H'040
H'060
H'080
H'0A0
H'0C0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'5C0
H'1C0
H'5E0
H'200
H'220

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