D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 211

IC SUPER H MPU ROMLESS 208LQFP

D6417709SHF200BV

Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417709SHF200BV

Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bits 2 and 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—The Number of Execution Times Break Enable (ETBE): Enable the execution-times
break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the
number of break conditions matches with the number of execution times that is specified by the
BETR register.
Bit 6: PCBB
0
1
Bit 3: SEQ
0
1
Bit 0: ETBE
0
1
Description
PC break of channel B is set before instruction execution
PC break of channel B is set after instruction execution
Description
Channels A and B are compared under the independent condition (Initial value)
Channels A and B are compared under the sequential condition (channel A, then
channel B)
Description
The execution-times break condition is masked on channel B
The execution-times break condition is enabled on channel B
Rev. 5.00, 09/03, page 165 of 760
(Initial value)
(Initial value)

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