D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 547
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 547 of 809
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15.3.6
Initialization: Initialize the SCI using the following procedure before sending or receiving data.
Initialization is also required for switching from transmit mode to receive mode or from receive
mode to transmit mode. Figure 15.5 shows a flowchart of the initialization process.
1. Clear TE and RE in the serial control register (SCSCR) to 0.
2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SCSSR).
3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits)
4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR). When the
5. Set the value corresponding to the bit rate in the bit rate register (SCBRR).
6. Set the clock source select bits (CKE1 and CKE0 bits) in the serial control register (SCSCR).
7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and
in the serial mode register (SCSMR). At this time also clear the CHR and MP bits to 0 and set
the STOP and PE bits to 1.
SMIF bit is set to 1, the TxD and RxD pins both switch from ports to SCI pins and become
high-impedance.
Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock
is output from the SCK pin.
RE bits simultaneously unless performing auto-diagnosis.
Data Transmission and Reception
Rev. 5.00, 09/03, page 501 of 760
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