D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 406
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 406 of 809
- Download datasheet (5Mb)
Rev. 5.00, 09/03, page 360 of 760
Bus cycle
Bus cycle
Burst Mode
Once the bus is obtained, the transfer is performed continuously until the transfer end
condition is satisfied. In external request mode with low level detection of the DREQ pin,
however, when the DREQ pin is driven high, the bus passes to the other bus master after the
DMAC transfer request that has already been accepted ends, even if the transfer end conditions
have not been satisfied.
Burst mode cannot be used when a serial communication interface (IrDA, SCI), or A/D
converter is the transfer request source. Figure 11.13 shows an example of burst mode timing.
DREQ
DREQ
CPU
CPU
Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode
Figure 11.13 Example of Transfer in Burst Mode
CPU
CPU
CPU
CPU
DMAC DMAC DMAC
DMAC DMAC
Read
Read
Write
Write
Bus returned to CPU
Read
CPU DMAC DMAC CPU
DMAC DMAC
Read
Write
Read
Write
DMAC
Write
CPU
CPU
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