D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 77

• Manufacturer Part Number: D6417709SHF200BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SHF200BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: For the addressing modes below that use a displacement (disp), the assembler descriptions
Addressing
Mode
PC-relative
Immediate
in this manual show the value before scaling ( 1, 2, or 4) is performed according to the
operand size. This is done to clarify the operation of the IC. Refer to the relevant assembler
notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12; PC-relative
Instruction
Format
Rn
#imm:8
#imm:8
#imm:8
Effective Address Calculation Method
Effective address is sum of register PC and
Rn contents.
8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended.
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
8-bit immediate data imm of TRAPA
instruction is zero-extended and multiplied by
4.
PC
R0
+
PC + R0
Rev. 5.00, 09/03, page 31 of 760
Calculation Formula
PC + Rn
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