D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 423
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Register Configuration
Table 11.7 summarizes the CMT register configuration.
Table 11.7 Register Configuration
Notes: 1. The only value that can be written to the CMF bit in CMCSR0 is 0 to clear the flag.
11.4.2
Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether compare
match counter 0 (CMCNT0) is operated or halted. It is initialized to H'0000 by a reset, but retains
its previous value in standby mode.
Bits 15 to 2—Reserved: These bits are always read as 0. The write value should alway be 0.
Bit 1—Reserved: This bit can be read or written. The write value should always be 0.
Name
Compare match timer start
register
Compare match timer
control/status register 0
Compare match counter 0
Compare match constant
register 0
Initial value:
Initial value:
2. When address translation by the MMU does not apply, the address in parentheses
Register Descriptions
should be used.
R/W:
R/W:
Bit:
Bit:
15
—
—
R
R
0
7
0
Abbreviation
CMSTR
CMCSR0
CMCNT0
CMCOR0
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
R/W
R/(W)
R/(W) *
R/W
R/W
12
—
—
1
R
R
0
4
0
Initial
Value
H'0000
H'0000
H'FFFF
H'0000
11
—
—
R
R
0
3
0
Rev. 5.00, 09/03, page 377 of 760
Address
H'04000070
(H'A4000070) *
H'04000072
(H'A4000072) *
H'04000074
(H'A4000074) *
H'04000076
(H'A4000076) *
10
—
—
R
R
0
2
0
2
2
2
2
R/W
—
—
R
9
0
1
0
Access Size
(Bits)
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
STR0
R/W
—
R
8
0
0
0
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