D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 634
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.2.2
The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins
PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function
is general output port, if the port is read the value of the corresponding PADR bit is returned
directly. When the function is general input port, if the port is read the corresponding pin level is
read. Table 19.2 shows the function of PADR.
PADR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Table 19.2 Port A Data Register (PADR) Read/Write Operations
PAnMD1
0
1
Rev. 5.00, 09/03, page 588 of 760
Initial value:
Port A Data Register (PADR)
PAnMD0
0
1
0
1
R/W:
Bit:
PA7DT
R/W
7
0
Pin State
Other function
(See table 18.1)
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
PA6DT
R/W
6
0
PA5DT
R/W
Read
PADR value
PADR value
Pin state
Pin state
5
0
PA4DT
R/W
4
0
Write
Value is written to PADR, but does not
affect pin state
Write value is output from pin
Value is written to PADR, but does not
affect pin state
Value is written to PADR, but does not
affect pin state
PA3DT
R/W
3
0
PA2DT
R/W
2
0
PA1DT
R/W
1
0
(n = 7 to 0)
PA0DT
R/W
0
0
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