HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 482

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Automatic Alignment of SCI Bit Rate
When started in boot mode, the H8/3437F measures the low period in asynchronous SCI data
transmitted from the host (figure 20.5). The data format is eight data bits, one stop bit, and no
parity bit. From the measured low period (9 bits), the H8/3437F computes the host’s bit rate. After
aligning its own bit rate, the H8/3437F sends the host 1 byte of H'00 data to indicate that bit-rate
alignment is completed. The host should check that this alignment-completed indication is
received normally and send one byte of H'55 back to the H8/3437F. If the alignment-completed
indication is not received normally, the H8/3437F should be reset, then restarted in boot mode to
measure the low period again. There may be some alignment error between the host’s and
H8/3437F’s bit rates, depending on the host’s bit rate and the H8/3437F’s system clock frequency.
To have the SCI operate normally, set the host’s bit rate to 2400, 4800, or 9600 bps
lists typical host bit rates and indicates the clock-frequency ranges over which the H8/3437F can
align its bit rate automatically. Boot mode should be used within these frequency ranges
Table 20.8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by
Host Bit Rate
9600 bps
4800 bps
2400 bps
Notes: *1 Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be
450
*2 Although the H8/3437F may also perform automatic bit-rate alignment with bit rate and
Figure 20.5 Measurement of Low Period in Data Transmitted from Host
used.
system clock combinations other than those shown in table 20.8, there will be a slight
difference between the bit rates of the host and the H8/3437F, and subsequent transfer
will not be performed normally. Therefore, only a combination of bit rate and system
clock frequency within one of the ranges shown in table 20.8 can be used for boot
mode execution.
H8/3437F
*1
Start
bit
D0
This low period (9 bits) is measured (H'00 data)
System Clock Frequencies Permitting Automatic Bit-Rate Alignment
by H8/3437F
8 MHz to 16 MHz
4 MHz to 16 MHz
2 MHz to 16 MHz
D1
D2
D3
D4
D5
D6
D7
Stop
bit
High for at
least 1 bit
*1
. Table 20.8
*2
.