HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 107

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.5
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt
requests, commands the CPU to start the hardware interrupt exception-handling sequence, and
furnishes the necessary vector number. Figure 4.4 shows a block diagram of the interrupt
controller.
The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected
for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared
to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These
interrupts can also all be masked by setting the CPU’s interrupt mask bit (I) to 1. Accordingly,
these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0.
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware
standby mode.
NMI interrupt
IRQ
IRQ0E
IRIC
IEIC
Note: *
0
flag
Interrupt Handling
For edge-sensed interrupts, these AND gates change to the circuit shown below.
IRQ
Figure 4.4 Block Diagram of Interrupt Controller
*
IRQ0E
0
IRQ
interrupt
IICI
interrupt
edge
0
IRQ
S
0
decision
Priority
flag
Q
IRQ
Interrupt
controller
Interrupt request
Vector number
0
interrupt
CPU
I (CCR)
75