HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 338

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HD64F3437TFI16V

Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F3437TFI16V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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13.3.7
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 13.11 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
306
SCL or
SDA input
signal
Sampling
clock
t: System clock
Noise Canceler
D
Sampling clock
Latch
C
Figure 13.11 Block Diagram of Noise Canceler
t
Q
D
Latch
C
Q
detector
Match
Internal
SCL or
SDA
signal

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