HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 353
HD64F3437TFI16V
Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F3437TFI16V.pdf
(755 pages)
Specifications of HD64F3437TFI16V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.2
14.2.1
SYSCR is an 8-bit read/write register which controls chip operations. Host interface functions are
enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for
information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset and in
hardware standby mode.
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the
host interface handles host-slave data transfers, operating in slave mode.
Bit 1: HIE
0
1
14.2.2
Bit
Initial value
Slave Read/Write
Host Read/Write
HICR is an 8-bit read/write register which controls host interface interrupts and the fast A
function. HICR is initialized to H'F8 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit
Initial value
Read/Write
Register Descriptions
System Control Register (SYSCR)
Host Interface Control Register (HICR)
SSBY
R/W
Description
The host interface is disabled
The host interface is enabled (slave mode)
7
0
—
—
—
7
1
STS2
R/W
6
0
—
—
—
6
1
STS1
R/W
5
0
—
—
—
5
1
STS0
R/W
4
0
—
—
—
4
1
XRST
3
1
R
—
—
—
3
1
NMIEG
IBFIE2
R/W
R/W
2
0
—
2
0
IBFIE1
R/W
HIE
R/W
—
1
0
1
0
(Initial value)
FGA20E
20
RAME
gate
R/W
R/W
—
0
1
0
0
321
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