HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 290

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HD64F3437TFI16V

Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F3437TFI16V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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12.3
12.3.1
The SCI supports serial data transfer in two modes. In asynchronous mode each character is
synchronized individually. In synchronous mode communication is synchronized with a clock
signal.
The selection of asynchronous or synchronous mode and the communication format depend on
SMR settings as indicated in table 12.7. The clock source depends on the settings of the C/A bit in
the SMR and the CKE1 and CKE0 bits in SCR as indicated in table 12.8.
Asynchronous Mode
Synchronous Mode
258
Data length: 7 or 8 bits can be selected.
A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be
selected. (These selections determine the communication format and character length.)
Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in
receive data, and the line-break condition can be detected.
SCI clock source: An internal or external clock source can be selected.
Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock
signal at the bit-rate frequency.
External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud
rate generator is not used.)
Communication format: The data length is 8 bits.
Overrun errors (ORER) can be detected in receive data.
SCI clock source: An internal or external clock source can be selected.
Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock
signal to external devices.
External clock: The on-chip baud rate generator is not used. The SCI operates on the input
serial clock.
Operation
Overview

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