HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 26

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 A/D Converter
15.1 Overview............................................................................................................................ 335
15.2 Register Descriptions......................................................................................................... 339
15.3 CPU Interface .................................................................................................................... 342
15.4 Operation ........................................................................................................................... 344
15.5 Interrupts............................................................................................................................ 350
15.6 Application Notes.............................................................................................................. 350
Section 16 D/A Converter
16.1 Overview............................................................................................................................ 355
16.2 Register Descriptions......................................................................................................... 358
16.3 Operation ........................................................................................................................... 360
Section 17 RAM
17.1 Overview............................................................................................................................ 361
17.2 Operation ........................................................................................................................... 362
Section 18 ROM (Mask ROM Version/ZTAT Version)
18.1 Overview............................................................................................................................ 363
18.2 Writer Mode (H8/3437, H8/3434)..................................................................................... 364
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15.1.1 Features ................................................................................................................ 335
15.1.2 Block Diagram...................................................................................................... 336
15.1.3 Input Pins.............................................................................................................. 337
15.1.4 Register Configuration ......................................................................................... 338
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 339
15.2.2 A/D Control/Status Register (ADCSR)................................................................ 340
15.2.3 A/D Control Register (ADCR)............................................................................. 342
15.4.1 Single Mode (SCAN = 0) ..................................................................................... 344
15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 346
15.4.3 Input Sampling and A/D Conversion Time.......................................................... 348
15.4.4 External Trigger Input Timing ............................................................................. 349
16.1.1 Features ................................................................................................................ 355
16.1.2 Block Diagram...................................................................................................... 356
16.1.3 Input and Output Pins........................................................................................... 357
16.1.4 Register Configuration............................................................................................ 357
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 358
16.2.2 D/A Control Register (DACR)............................................................................. 358
17.1.1 Block Diagram...................................................................................................... 361
17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) ....................... 362
17.2.1 Expanded Modes (Modes 1 and 2)....................................................................... 362
17.2.2 Single-Chip Mode (Mode 3) ................................................................................ 362
18.1.1 Block Diagram...................................................................................................... 364
18.2.1 Writer Mode Setup ............................................................................................... 364
................................................................................................................... 361
................................................................................................. 335
................................................................................................. 355
.......................................... 363