MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 54

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 1 MC9S12NE64 Device Overview
1.2.3.40 PL6 — Port L I/O Pin 6
PL6 is a general-purpose I/O pin. While in reset and immediately out of reset, the PL6 pin is configured
as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description
chapter for information about pin configurations.
1.2.3.41 PL5 — Port L I/O Pin 5
PL5 is a general-purpose I/O pin. While in reset and immediately out of reset, the PL5 pin is configured
as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description
chapter for information about pin configurations.
1.2.3.42 PL4 / COLLED — Port L I/O Pin 4
PL4 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the collision status signal (COLLED). While in reset and
immediately out of reset the PL4 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.43 PL3 / DUPLED — Port L I/O Pin 3
PL3 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the duplex status signal (DUPLED). While in reset and
immediately out of reset, the PL3 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.44 PL2 / SPDLED — Port L I/O Pin 2
PL2 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the speed status signal (SPDLED). While in reset and
immediately out of reset, the PL2 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.45 PL1 / LNKLED — Port L I/O Pin 1
PL1 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the link status signal (LNKLED). While in reset and
immediately out of reset, the PL1 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
MC9S12NE64 Data Sheet, Rev 1.0
54
Freescale Semiconductor