MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 497

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.4.2.6.3
In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored
in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing
modes where storing only the destination address would not provide all information required for a user to
determine where his code was in error.
18.4.2.6.4
This mode is intended to allow a host computer to poll a running target and provide a histogram of program
execution. Each read of the trace buffer address will return the address of the last instruction executed. The
DBGCNT register is not incremented and the trace buffer does not get filled. The ARM bit is not used and
all breakpoints and all other debug functions will be disabled.
18.4.2.7
The storage memory is a 64 words deep by 16-bits wide dual port RAM array. The CPU accesses the RAM
array through a single memory location window (DBGTBH:DBGTBL). The DBG module stores trace
information in the RAM array in a circular buffer format. As data is read via the CPU, a pointer into the
RAM will increment so that the next CPU read will receive fresh information. In all trigger modes except
for event-only and detail capture mode, the data stored in the trace buffer will be change-of-flow addresses.
change-of-flow addresses are defined as follows:
In the event-only trigger modes only the 16-bit data bus value corresponding to the event is stored. In the
detail capture mode, address and then data are stored for all cycles except program fetch (P) and free (f)
cycles.
18.4.2.8
18.4.2.8.1
Storing with begin-trigger can be used in all trigger modes. When DBG mode is enabled and armed in the
begin-trigger mode, data is not stored in the trace buffer until the trigger condition is met. As soon as the
trigger condition is met, the DBG module will remain armed until 64 words are stored in the trace buffer.
If the trigger is at the address of the change-of-flow instruction the change-of-flow associated with the
trigger event will be stored in the trace buffer.
18.4.2.8.2
Storing with end-trigger cannot be used in event-only trigger modes. When DBG mode is enabled and
armed in the end-trigger mode, data is stored in the trace buffer until the trigger condition is met. When
the trigger condition is met, the DBG module will become de-armed and no more data will be stored. If
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Source address of conditional branches (long, short, BRSET, and loop constructs) taken
Destination address of indexed JMP, JSR, and CALL instruction
Destination address of RTI, RTS, and RTC instructions
Vector address of interrupts except for SWI and BDM vectors
Storage Memory
Storing Data in Memory Storage Buffer
Detail Mode
Profile Mode
Storing with Begin-Trigger
Storing with End-Trigger
MC9S12NE64 Data Sheet, Rev. 1.1
Functional Description
497