MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 309

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.2.1
The PHY provides this input clock, which is used as a timing reference for MII_TXD, MII_TXEN, and
MII_TXER. It operates at 25% of the transmit data rate (25 MHz for 100 Mbps or 2.5 MHz for 10 Mbps).
The EMAC bus clock frequency must be greater-than or equal-to MII_TXCLK.
11.2.2
MII_TXD[3:0] is a transmit nibble of data to be transferred from the EMAC to the PHY. The nibble is
synchronized to the rising edge of MII_TXCLK. When MII_TXEN is asserted, the PHY accepts
MII_TXD[3:0], and at all other times, MII_TXD[3:0] is ignored. MII_TXD[0] is the least significant bit.
Table 11-1
11.2.3
Assertion of this output signal indicates that there are valid nibbles being presented on the MII and the
transmission can start. This signal is asserted with the first nibble of the preamble, remains asserted until
all nibbles to be transmitted have been presented to the PHY, and is negated following the final nibble of
the frame.
11.2.4
Assertion of this output signal for one or more clock cycles while MII_TXEN is asserted causes the PHY
to transmit one or more illegal symbols. MII_TXER is asserted if the ABORT command is issued during
a transmit. This signal transitions synchronously with respect to MII_TXCLK.
11.2.5
The PHY provides this input clock, which is used as a timing reference for MII_RXD, MII_RXDV, and
MII_RXER. It operates at 25% of the receive data rate (25 MHz for 100 Mbps or 2.5 MHz for 10 Mbps).
The EMAC bus clock frequency must be greater-than or equal-to MII_RXCLK.
Freescale Semiconductor
MII_TXCLK — MII Transmit Clock
MII_TXD[3:0] — MII Transmit Data
summarizes the permissible encoding of MII_TXD[3:0], MII_TXEN, and MII_TXER.
MII_TXEN — MII Transmit Enable
MII_TXER — MII Transmit Coding Error
MII_RXCLK — MII Receive Clock
MII_TXEN
Table 11-1. Permissible Encoding of MII_TXD, MII_TXEN, and MII_TXER
0
0
1
1
MII_TXER
0
1
0
1
MC9S12NE64 Data Sheet, Rev. 1.1
0000 through 1111
0000 through 1111
0000 through 1111
0000 through 1111
MII_TXD[3:0]
Transmit error propagation
Normal data transmission
Normal interframe
Indication
Reserved
External Signal Description
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