MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 360
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MC9S12NE64VTUE
Manufacturer Part Number
MC9S12NE64VTUE
Description
IC MCU 64K FLASH EEPROM 80-TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64VTUE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Processor Series
S12N
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
125 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12NE64E, DEMO9S12NE64E
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Total Internal Ram Size
8KB
# I/os (max)
70
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
2.625/3.465V
Operating Supply Voltage (min)
2.357/2.375/3.135V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
TQFP
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12NE64VTUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12NE64VTUE
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 12 Ethernet Physical Transceiver (EPHYV2)
TAF10HD — 10BASE-T Half-Duplex
12.3.3.6 Auto Negotiation Link Partner Ability (Base Page)
Figure 12-11
the MI and will be written by the auto-negotiation process when it receives a link code word advertising
the capabilities of the link partner. This register has a dual purpose: exchange of base page information as
shown in
MII Register Address 5 (%00101) (Base Page)
Read:
Write:
NXTP — Next Page
ACK — Acknowledge
RFLT — Remote Fault
FLCTL — Flow Control
TAF100T4 — 100BASE-T4 Full-Duplex
TAF100FD — 100BASE-TX Full-Duplex
360
RESET:
W
This function is not implemented in the EPHY.
R
1 = 10BASE-T half-duplex capable
0 = Not 10BASE-T half-duplex capable
1 = Link partner capable of sending next pages
0 = Link partner not capable of sending next pages
1 = Link Partner has received link code word
0 = Link Partner has not received link code word
1 = Remote fault
0 = No remote fault
1 = Advertises implementation of the optional MAC control sublayer and pause function as
0 = No MAC-based flow control
1 = Link partner is 100BASE-T4 capable
0 = Link partner is not 100BASE-T4 capable
1 = Link partner is 100BASE-TX full-duplex capable
0 = Link partner is not 100BASE-TX full-duplex capable
Figure
NXTP
15
specified in IEEE standard clause 31 and anex 31B of 802.3. Setting FLCTL has no effect on
the PHY.
X
shows the contents of the A/N link partner ability register. The register can only be read by
= Unimplemented or Reserved
ACK
12-11, and exchange of next page information as shown in
14
Figure 12-11. Auto Negotiation Link Partner Ability Register (Base Page)
X
RFLT
13
X
12
X
TAF[1:0]
11
X
MC9S12NE64 Data Sheet, Rev. 1.1
FCTL
10
X
100T4
TAF
X
9
100FD
TAF
X
8
100HD
TAF
X
7
10FD
TAF
X
6
10HD
TAF
X
5
Figure
X
4
SELECTORFIELD[4:0]
12-12.
X
3
Freescale Semiconductor
X
2
X
1
0
X
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