ZLF645E0Q2064G Zilog, ZLF645E0Q2064G Datasheet - Page 89

• Manufacturer Part Number: ZLF645E0Q2064G
• Description: IC MCU 64K FLASH 1K RAM 20-QFN
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0Q2064G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4723

PS026407-0408
1
0
Idle state
of line
1
0
Idle state
of line
Data Format
Transmitting Data Using Polled Method
Start
The UART transmits and receives data in an 8-bit data format, with the least significant bit
(lsb) occurring first. An even- or odd-parity bit can be optionally added to the data stream.
Each character begins with an active Low Start bit and ends with either 1 or 2 active High
Stop bits.
UARTs with or without parity, respectively.
Follow the steps below to transmit data using the polled method of operation:
1. Write to the Baud Rate Generator Constant (BCNST) register, address
2. Write 0 to bit 6 of the P01M register.
3. Write to the UART Control register (UCTL) to:
Start
appropriate baud rate.
(a) Set the transmit enable bit, UCTL[7], to enable the UART for data transmission.
(b) If parity is appropriate, set the parity enable bit, UCTL[4] to 1 and select either
Figure 23. UART Asynchronous Data Format without Parity
Bit 0
Figure 24. UART Asynchronous Data Format with Parity
LSB
even- or odd-parity (UCTL[3]).
Figure 23
Bit 0
LSB
Bit 1
Bit 1
and
Bit 2
Figure 24
Bit 2
Bit 3
Data field
Bit 3
Data field
display the asynchronous data format employed by the
Bit 4
Bit 4
Bit 5
Bit 5
Bit 6
Bit 6
ZLF645 Series Flash MCUs
Bit 7
Bit 7
Product Specification
MSB
Bit 7
MSB
Stop bit(s)
1
0F4h
Stop bit(s)
2
1
2
, to set the
Operation
81