ZLF645E0Q2064G Zilog, ZLF645E0Q2064G Datasheet - Page 135

• Manufacturer Part Number: ZLF645E0Q2064G
• Description: IC MCU 64K FLASH 1K RAM 20-QFN
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0Q2064G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4723

Table 66. Interrupt Mask Register (IMR)
PS026407-0408
Bit
Field
Reset
R/W
Address
Bit Position
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Interrupt Mask Register
Master Interrupt
Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When
reset, all interrupts are disabled. When writing 1 to bit 7, you must also execute the EI
instruction to enable interrupts (see
Value
Enable
R/W
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
7
0
Description
Master Interrupt Enable
Use only DI and EI instructions to alter this bit. Always disable interrupts (DI
instruction) before writing this register.
All interrupts are disabled.
Interrupts are enabled/disabled individually in bits [5:0].
Reserved
Reads are undefined; Must be written to 1.
Disables IRQ5.
Enables IRQ5.
Disables IRQ4.
Enables IRQ4.
Disables IRQ3.
Enables IRQ3.
Disables IRQ2.
Enables IRQ2.
Disables IRQ1.
Enables IRQ1.
Disables IRQ0.
Enables IRQ0.
Reserved
—
X
6
Bank Independent: FBh; Linear: 0FBh
Enable
IRQ5
R/W
X
5
Table
Enable
IRQ4
R/W
X
4
66).
Enable
IRQ3
R/W
X
3
ZLF645 Series Flash MCUs
Enable
IRQ2
R/W
X
2
Product Specification
Interrupt Mask Register
Enable
IRQ1
R/W
X
1
Enable
IRQ0
R/W
X
0
127