ZLF645E0Q2064G Zilog, ZLF645E0Q2064G Datasheet - Page 132

• Manufacturer Part Number: ZLF645E0Q2064G
• Description: IC MCU 64K FLASH 1K RAM 20-QFN
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0Q2064G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4723

Table 64. Interrupt Priority Register (IPR)
PS026407-0408
Bit
Field
Reset
R/W
Address
Bit Position
[7:6]
[5]
Interrupt Priority Register
Reserved
X
7
Programming bits for the Interrupt Edge Select are located in the IRQ register (R250),
bit 6 and bit 7.
Table 63. Interrupt Request Register
The Interrupt Priority register (see
priority. Interrupts are divided into three groups of two—Group A, Group B, and Group C.
IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts
IRQ5, IRQ1, and IRQ0 occur simultaneously when IPR[4:3,0]=001b, the interrupts are
serviced in the following order: IRQ1, IRQ0, IRQ5.
IPR bits 5, 2, and 1 determine which interrupt within each group has higher priority.
Value
IRQ Bit
7
0
0
1
1
Note: F = Falling Edge; R = Rising Edge.
—
0
1
—
X
6
Description
Reserved
Reads are undefined; writes must be 00b.
Group A Priority (IRQ3, IRQ5)
IRQ5 > IRQ3
IRQ3 > IRQ5
6
0
1
0
1
Group A
Priority
Table 63
W
X
5
Interrupt Edge
IRQ2 (P31)
F
F
R
R/F
Bank Independent: F9h; Linear: 0F9h
provides the configuration.
Group Priority
X
4
[2:1]
W
Table
IRQ0 (P32)
F
R
F
R/F
X
3
64) defines which interrupt holds the highest
Group B
Priority
W
X
2
ZLF645 Series Flash MCUs
Group C
Priority
W
X
1
Product Specification
Interrupt Priority Register
Group Priority
[0]
W
X
0
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