AT89C51RE2-SLSUM Atmel, AT89C51RE2-SLSUM Datasheet - Page 156

• Manufacturer Part Number: AT89C51RE2-SLSUM
• Description: MCU 8BIT FLASH 2.7-5.5V 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Package: 44PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

OverRun Condition
Interrupts
156
AT89C51RE2
Figure 64. Mode Fault Conditions in Slave Mode
Note:
This error mean that the speed is not adapted for the running application:
An OverRun condition occurs when a byte has been received whereas the previous one has not
been read by the application yet.
The last byte (which generate the overrun error) does not overwrite the unread data so that it
can still be read. Therefore, an overrun error always indicates the loss of data.
Three SPI status flags can generate a CPU interrupt requests:
Table 114. SPI Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been
completed. SPIF bit generates transmitter CPU interrupt request only when SPTEIE is disabled.
Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent with the
mode of the SPI (in both master and slave modes).
Serial Peripheral Transmit Register empty flag, SPTE: This bit is set when the transmit buffer is
empty (other data can be loaded is SPDAT). SPTE bit generates transmitter CPU interrupt
request only when SPTEIE is enabled.
Flag
SPIF (SPI data transfer)
MODF (Mode Fault)
SPTE (Transmit register empty)
Note: While using SPTE interruption for “burst mode” transfers (SPTEIE=’1’), the user soft-
ware application should take care to clear SPTEIE, during the last but one data reception (to
be able to generate an interrupt on SPIF flag at the end of the last data reception).
when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode
because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
MOSI
SCK cycle #
SCK
(from master)
(from master)
MISO
(from slave)
SS
(slave)
1
z
0
1
z
0
1
z
0
1
z
0
0
MODF detected
MSB
Request
SPI Transmitter Interrupt Request
SPI mode-fault Interrupt Request
SPI transmit register empty Interrupt Request
0
MSB
MSB
1
MODF detected
B6
B6
2
B5
3
B4
4
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