AT89C51RE2-SLSUM Atmel, AT89C51RE2-SLSUM Datasheet - Page 154

• Manufacturer Part Number: AT89C51RE2-SLSUM
• Description: MCU 8BIT FLASH 2.7-5.5V 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Package: 44PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 62. Queuing Transmission In Master Mode
154
MOSI
MISO
Data
SPTE
SCK
AT89C51RE2
MSB
MSB
Byte 1
B6
B6
When a transmission is in progress a new data can be queued and sent as soon as transmission
has been completed. So it is possible to transmit bytes without latency, useful in some
applications.
The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user
application can write SPDAT with the data to be transmitted until the SPTE becomes cleared.
Figure 62 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is immedi-
ately sent on the bus. Meanwhile an other byte is prepared (and the SPTE is cleared), it will be
sent at the end of the current transmission. The next data must be ready before the end of the
current transmission.
In slave mode it is almost the same except it is the external master that start the transmission.
Also, in slave mode, if no new data is ready, the last value received will be the next data byte
transmitted.
BYTE 1 under transmission
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
Byte 2
LSB
LSB MSB
MSB
B6
B6
BYTE 2 under transmission
B5
B5
B4
B4
B3
B3
Byte 3
B2
B2
B1
B1
LSB
LSB
7663E–8051–10/08