AT89C51RE2-SLSUM Atmel, AT89C51RE2-SLSUM Datasheet - Page 152

• Manufacturer Part Number: AT89C51RE2-SLSUM
• Description: MCU 8BIT FLASH 2.7-5.5V 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Package: 44PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Master Mode
Slave Mode
Transmission Formats
152
AT89C51RE2
When the Master device transmits data to the Slave device via the MOSI line, the Slave device
responds by sending data to the Master device via the MISO line. This implies full-duplex trans-
mission with both data out and data in synchronized with the same clock (Figure 58).
Figure 58. Full-Duplex Master-Slave Interconnection
The SPI operates in Master mode when the Master bit, MSTR
Only one Master SPI device can initiate transmissions. Software begins the transmission from a
Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register
is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on
MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from
the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer
data flag, SPIF, in SPSCR becomes set. At the same time that SPIF becomes set, the received
Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF
by reading the Serial Peripheral Status register (SPSCR) with the SPIF bit set, and then reading
the SPDAT.
The SPI operates in Slave mode when the Master bit, MSTR
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must
be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from the Mas-
ter SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive
data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software
must then read the SPDAT before another Byte enters the shift register
complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI
starts a transmission. If the write to the data register is late, the SPI transmits the data already in
the shift register from the previous transmission.
Software can select any of four combinations of serial clock (SCK) phase and polarity using two
bits in the SPCON: the Clock Polarity (CPOL
the default SCK line level in idle state. It has no significant effect on the transmission format.
CPHA defines the edges on which the input data are sampled and the edges on which the out-
put data are shifted (Figure 59 and Figure 60). The clock phase and polarity should be identical
for the Master SPI device and the communicating Slave device.
1.
2.
3.
4.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Mas-
The SPI Module should be configured as a Slave before it is enabled (SPEN set).
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
ter SPI should be configured before the Slave SPI.
Clock Generator
SPI
Master MCU
8-bit Shift register
MOSI
SCK
SS
MISO
(4)
VDD
) and the Clock Phase (CPHA
MOSI
MISO
SCK
VSS
SS
(1)
8-bit Shift register
, in the SPCON register is set.
(2)
Slave MCU
, in the SPCON register is
(3)
. A Slave SPI must
4
). CPOL defines
7663E–8051–10/08