AT89C51RE2-SLSUM Atmel, AT89C51RE2-SLSUM Datasheet - Page 136
![MCU 8BIT FLASH 2.7-5.5V 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT89C51RE2-SLSUM
Manufacturer Part Number
AT89C51RE2-SLSUM
Description
MCU 8BIT FLASH 2.7-5.5V 44-PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RE2-SLSUM.pdf
(187 pages)
Specifications of AT89C51RE2-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
SPI/TWI/UART
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
8 KB
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89OCD-01
Minimum Operating Temperature
- 40 C
Cpu Family
89C
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
8KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51RE2-SLSUM
Manufacturer:
HONEYWELL
Quantity:
101
Miscellaneous States
Notes
136
AT89C51RE2
its own slave address followed by the data direction bit which must be at logic 1 (R) for
TWI to operate in the slave transmitter mode. After its own slave address and the R bit
have been received, the serial interrupt flag is set and a valid status code can be read
from SSCS. This status code is used to vector to an interrupt service routine. The appro-
priate action to be taken for each of these status code is detailed in Table . The slave
transmitter mode may also be entered if arbitration is lost while the TWI module is in the
master mode.
If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the
transfer and enter state C0h or C8h. the TWI module is switched to the not addressed
slave mode and will ignore the master receiver if it continues the transfer. Thus the mas-
ter receiver receives all 1’s as serial data. While AA is reset, the TWI module does not
respond to its own slave address. However, the 2-wire bus is still monitored and
address recognition may be resume at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the TWI module from the 2-wire bus.
There are two SSCS codes that do not correspond to a define TWI hardware state
(Table 106 ). These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not set yet. This occurs between other states and when the TWI module is not
involved in a serial transfer.
Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus
error is caused when a START or a STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions happen during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To
recover from a bus error, the STO flag must be set and SI must be cleared. This causes
the TWI module to enter the not addressed slave mode and to clear the STO flag (no
other bits in SSCON are affected). The SDA and SCL lines are released and no STOP
condition is transmitted.
the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock
line) and SDA (serial data line). To avoid low level asserting on these lines when the
TWI module is enabled, the output latches of SDA and SLC must be set to logic 1.
Table 101. Bit Frequency Configuration
CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
F
OSCA
0.5 <. < 62.5
= 12 MHz
53.5
62.5
100
200
Bit Frequency ( kHz)
47
75
-
F
OSCA
0.67 <. < 83
133.3
266.6
62.5
71.5
= 16 MHz
100
83
-
(reload value range: 0-254 in mode 2)
96 · (256 - reload valueTimer 1)
F
OSCA
Unused
divided by
256
224
192
160
120
60
7663D–8051–10/08